As CMOS technology is scaled down into deep submicron regime, the advanced processes, such as thinner gate oxide, shorter channel length, shallower source/drain junction, lightly doped drain CLDD) structure and silicided diffusion, ESD robustness of the deep submicron CMOS IC is degraded to a great extent. The descriptions of the related techniques are disclosed in T. L. Polgreen and A. Chatterjee, "Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow", IEEE Trans. on Electron Devices, vol. 39, no. 2, pp. 379-388, Feb. 1992; C. D. Lien, "Electrostatic Discharge protection circuit", U.S. Pat. No. 5,086,365, Feb. 1992; C. Duvvury and C. Diaz, "Dynamic gate coupling of NMOS for efficient output ESD protection", Proc. of IRPS, pp. 141-150, 1992; and C. Duvvury, C. Diaz and T. Haddock, "Achieving uniform nMOS device power distribution for submicron ESD reliability", in Tech. Dig. of IEDM, pp. 131-134, 1992. To achieve the desired ESD robustness, an ESD protection circuit in submicron CMOS technologies having dimensions much larger than the dimensions of the protection circuit in conventional submicron CMOS technologies is generally necessary for each input or output pad. Such a necessity, however, is impractical for the high-pin-count submicron CMOS IC which is more and more popular nowadays. As known to those skilled in the art, the total layout area of a chip (die size) increases with the increase of the pad pitch. If the dimensions of the ESD protection circuit are too large, the pad pitch will have to be enlarged and the total layout area will accordingly be increased. It is difficult for the submicron CMOS IC to perform ESD robustness within small layout area.
In addition, several ESD protection circuits are provided for improving ESD reliability of CMOS IC, such as those disclosed in R. Co, K. F. Lee and K. W. Ouyang, "Capacitively induced electrostatic discharge protection circuit", U.S. Pat. No. 5,173,755, Dec. 1992; Y. H. Wei, "Output pad electrostatic discharge protection circuit for MOS device", U.S. Pat. No. 5,208,719, May 1993; G. L. Mortensen, "Electrostatic discharge protection device and a method for simultaneously forming MOS devices with both lightly doped and non lightly doped source and drain regions", U.S. Pat. No. 5,208,475, May 1993; K. F. Lee, "Power rail ESD protection circuit", U.S. Pat. No. 5,237,395, Aug. 1993; and D. S. Puar, "Shunt circuit for electrostatic discharge protection", U.S. Pat. No. 5,287,241, Feb. 1994. However, the above protection devices need other auxiliary devices (such as the field-oxide device, thin-oxide NMOS and PMOS, or zener diode) which generally occupy more extra layout area to perform ESD protection. Moreover, the gate oxide is scaled down to only 90.+-.10 .ANG. in a 0.5-.mu.m 3-V CMOS technology, and the gate-oxide breakdown voltage is around 9.about.12V in such submicron CMOS technology. The initial ram-on voltage of NMOS/PMOS device with its gate shorted to its source depends on the snapback voltage generated in accordance with the punchthrough or the avalanche breakdown at the drain. The snapback voltage of short-channel NMOS/PMOS device conventionally used for protecting the input gate, however, typically has a value of about 10.about.11V in such a 0.5-.mu.m 3-V CMOS technology. It possibly leads to the rupture of the gate oxide and accordingly causes damage on the input gate because the snapback voltage of short-channel NMOS/PMOS devices is near or even higher than the gate-oxide breakdown voltage. Thus, the reduction of the snapback voltage is also an important factor for the design of the ESD protection circuit. A conventional process for reducing the snapback voltage is performed by using an additional ESD-implantation step. Unfortunately, the addition of the implantation step increases the complexity of submicron CMOS technology as well as the fabrication cost.